It's routing time! Everyone's favourite layout optimization game. Let's see how many times I can flip a footprint! Got some errors when loading up the footprints from the schematic ``` Error: J2 pad A4 not found in tahnok:MOLEX_2169900003_usb_c. Error: J2 pad A9 not found in tahnok:MOLEX_2169900003_usb_c. Error: J2 pad B4 not found in tahnok:MOLEX_2169900003_usb_c. Error: J2 pad B9 not found in tahnok:MOLEX_2169900003_usb_c. Error: J2 pad A1 not found in tahnok:MOLEX_2169900003_usb_c. Error: J2 pad A12 not found in tahnok:MOLEX_2169900003_usb_c. Error: J2 pad B1 not found in tahnok:MOLEX_2169900003_usb_c. Error: J2 pad B12 not found in tahnok:MOLEX_2169900003_usb_c. ``` Fixed by deleting some pins on the schematic and renaming others. A4 and B9 are connected to one pin on this connector. Now I'm trying to move stuff around to make routing cleaner. I'm also trying to figure out what I need to worry about for the D+/D- differential pair. Digikey has an article about this: https://www.digikey.ca/en/maker/projects/how-to-route-differential-pairs-in-kicad-for-usb/45b99011f5d34879ae1831dce1f13e93 Pretty in depth, looks like they have pretty large traces. Also routing over unbroken ground plane might be tricky. The only problem is how to get the traces around the VBUS thing. I also need to figure out which "direction" the ExpressCard connector faces. Another question: is it better to route power or signals through vias? https://electronics.stackexchange.com/questions/450585/which-is-the-preferred-approach-to-pcb-layout-for-signal-vs-power-traces-in-anal Seems like doesn't matter with chonky enough vias. Now, what's a chonky enough via? Maybe I can learn some tricks from the [Tangara schematics](https://git.sr.ht/~jacqueline/tangara-hw)