Ok, so for the panel I can get my hands on, I need to use the following pins for the "34 pin" epaper connector | epaper pin | epaper signal | epaper description | soc ball name | soc signal name | soc description | notes | | ---------- | ------------- | ----------------------------------- | ------------- | ----------------- | ------------------------------------- | ------------------------------------------------------------- | | 1 | VNEG | Negative power supply source driver | n/a | n/a | | -15V | | 2 | VEE | Negative power supply gate driver | n/a | n/a | | -20V | | 3 | VSS | | | | | gnd | | 4 | NC | | | | | | | 5 | NC | | | | | | | 6 | VDD | | | | | 1.8V | | 7 | VSS | | | | | | | 8 | XCL | clock source driver | EIM_D31 | EPDC_SDCLK_P | Positive Source Driver-Shift Clock | there's a negative version of this too... EPDC_SDCLK_N | | 9 | VSS | | | | | | | 10 | XLE | latch enable source driver | EIM_DA1 | EPDC_SDLE | Source Driver-Latch Enable | | | 11 | XOE | output enable source driver | EIM_D27 | EPDC_SDOE | Source Driver-Output Enable | | | 12 | XSTL | Start pulse source driver | EPDC_SDCE0 | EIM_DA4 / EIM_EB3 | Source Driver-Chip-enable/Start-pulse | connected to 2 pads (weird) and there's another 8 I could use | | 13 | D0 | Data signal source driver | EPDC_DATA00 | EIM_A16 | Source Driver-Shift signal | | | 14 | D1 | Data signal source driver | EPDC_DATA01 | EIM_DA10 | Source Driver-Shift signal | | | 15 | D2 | Data signal source driver | EPDC_DATA02 | EIM_DA12 | Source Driver-Shift signal | | | 16 | D3 | Data signal source driver | EPDC_DATA03 | EIM_DA11 | Source Driver-Shift signal | | | 17 | D4 | Data signal source driver | EPDC_DATA04 | EIM_LBA | Source Driver-Shift signal | | | 18 | D5 | Data signal source driver | EPDC_DATA05 | EIM_EB2 | Source Driver-Shift signal | | | 19 | D6 | Data signal source driver | EPDC_DATA06 | EIM_CS0 | Source Driver-Shift signal | | | 20 | D7 | Data signal source driver | EPDC_DATA07 | EIM_RW | Source Driver-Shift signal | | | 21 | VCOM | common conection | | | | panel specific | | 22 | NC | | | | | | | 23 | NC | | | | | | | 24 | NC | | | | | | | 25 | NC | | | | | | | 26 | VSS | ground | | | | | | 27 | MODE1 | Output mode selection gate driver | | | | ?? maybe GPIO? | | 28 | CKV | Clock gate driver | EPDC_GDCLK | EIM_A21 | Gate driver clock | | | 29 | SPV | Start pulse gate driver | EPDC_GDSP | EIM_A22 | Gate driver start pulse | | | 30 | NC | | | | | | | 31 | Border | border connection | EPDC_BDR0 | EIM_DA2 | Panel-Border Control (SW controlled) | maybe optional? | | 32 | VSS | | | | | | | 33 | VPOS | Positive power supply source driver | | | | +15V | | 34 | VGG | Positive power supply gate driver | | | | +25V | Still confused about EPDC_SDCLK_P vs EPDC_SDCLK_N. Seems like I want P but maybe N if clock stuff matters. Gonna find out I guess! Gotta look more into MODE1, let's see what EPDIY has to say about it. Maybe it's GDOE? Aside, this TPS651851RSLR epaper PMIC from EPDIY looks good for generating the voltages I'll need and is only a few dollars. https://www.ti.com/product/TPS65185/part-details/TPS651851RSLR Note STV is hooked up to SPV, probably an alias. Claude code analysis: Based on the code analysis, ep_mode is a display control pin in the EPD (E-Paper Display) driver system. Here's what it does: ep_mode is a boolean control signal that works in conjunction with the output enable (ep_output_enable) pin to control the EPD gate driver operation. From the code at src/epd_board.c:36-44: - ep_mode is set together with ep_output_enable in the epd_set_mode() function - Both pins are controlled simultaneously and set to the same state - It's part of the display control register state (epd_ctrl_state_t) From the board definitions (like epd_board_v6.c:26), ep_mode is mapped to CFG_PIN_MODE which connects to a PCA9555 I/O expander pin. Usage: - Initialization: Set to false during epd_control_reg_init() - Power down: Set to false during epd_control_reg_deinit() - Operation: Controlled via epd_set_mode(bool state) which sets both ep_mode and ep_output_enable to the same value This suggests ep_mode is indeed related to gate driver output enable control, working alongside the main output enable pin to properly sequence the EPD gate driver operation.